1. Field of the Invention
The present invention relates to voltage generation circuits having a boost function. More specifically, the present invention provides a configuration of a voltage generation circuit capable of preventing excessive boosting of an output voltage even if the circuit is used at wide-ranging power supply voltage levels and suppressing a standby current in a period other than a boosting operation period, and a configuration of a semiconductor memory device provided therewith.
2. Description of the Background Art
With active development of devices requiring lower power consumption such as portable devices, semiconductor products have operated at lower voltage.
In a semiconductor memory device performing electrical data reading, erasing, writing and the like such as a flash memory, electrical storage data stored in a memory cell is generally read to a data line such as a bit line by applying an "H" level voltage to a word line. In order to achieve both lower voltage operation and higher speed data reading operation, it is essential that the "H" level voltage applied when a word line is to be driven is a voltage obtained by boosting a power supply voltage.
A circuit for generating the boosted voltage is called a word line boost circuit and provided in a semiconductor memory device. It is necessary to design the word line boost circuit so as not to uselessly consume power by operating the circuit only during a period in which generation of a boosted voltage is necessary and inactivating the circuit during other periods such as a standby period.
Semiconductor products have various power supply voltage levels according to their specifications. For example, the current flash memory market has roughly three types of power supply voltage ranges, that is, the versions of Vcc=1.6V.about.2.2V and Vcc=2.2V.about.2.7V which are regarded as lower power supply voltage versions, and the currently major version of Vcc=2.7V.about.3.6V.
In order to accommodate such various types of power supply voltage ranges, it is necessary to adjust boost capability according to a power supply voltage level in a word line boost circuit provided in a memory. Considering the case of the above described flash memory, it is necessary to switch boost capability according to power supply voltage range so that the boost capability is set to be larger for the Vcc=1.6V.about.2.2V version, smaller for the Vcc=2.2V.about.2.7V version, and boosting is not carried out for the Vcc=2.7V.about.3.6V version.
Such a method is adopted for switching the boost capability that the capacitance value of a boost capacitor provided in a word line boost circuit is separately provided by changing a mask pattern in a semiconductor device manufacturing process.
When the boost capability is switched by mask pattern changes, however, it is disadvantageously required that different masks are prepared and undergone separate manufacturing processes according to the power supply voltage range of a flash memory.
Otherwise, a power supply voltage level is detected and the capacitance value of a boost capacitor is made variable according to the power supply voltage level as a method of switching the boost capability according to the value of a power supply voltage.
FIG. 8 is a circuit diagram showing a configuration of a conventional voltage generation circuit 300 used as a word line boost circuit for generating a boosted voltage according to a power supply voltage level by adopting the above described method.
Referring to FIG. 8, voltage generation circuit 300 is a circuit for setting the voltage level Vbst of a voltage supply node 340 at one of a power supply voltage Vcc and a boosted voltage obtained by boosting Vcc. A boost control signal BST is activated to the "H" level when boosting is necessary and inactivated to the "L" level when boosting is not necessary.
Voltage generation circuit 300 includes a Vcc level detection circuit 305 receiving power supply voltage Vcc and setting a Vcc level signal LVL at the "H" level or the "L" level according to comparison between Vcc and a prescribed voltage, a boost circuit 310 transmitting one of power supply voltage Vcc and the boosted voltage to an output transistor 330 according to boost control signal BST and control signal LVL, a gate boost circuit 320 boosting the gate voltage of output transistor 330 according to boost control signal BST, and an output transistor 330 receiving an output of gate boost circuit 320 at its gate and provided to connect boost circuit 310 and voltage supply node 340.
Boost circuit 310 includes a delay circuit 312 receiving boost control signal BST, applying delay time td to boost control signal BST, and outputting delayed boosted control signal BST, a boost capacitance switch circuit 314 switching the capacitance value of a capacitor, which is used for boosting, according to the delayed boost control signal and Vcc level signal LVL, and a voltage switch circuit 315 transmitting one of power supply voltage Vcc and the boosted voltage as an output of boost capacitance switch circuit 314 to output transistor 330 according to delayed boost control signal BST.
Boost capacitance switch circuit 314 has P type MOS transistors Q21, Q22 and an N type MOS transistor Q23 connected in series between a power supply line 342 and a ground line 344. The gates of transistors Q21 and Q23 are supplied with delayed and inverted boost control signal BST which is an output of an inverter IV11. The gate of transistor Q22 is supplied with Vcc level signal LVL.
Boost capacitance switch circuit 314 also has a capacitor Cb1 connected between an internal node N21 and the output node of an inverter IV12, and a boost capacitor Cb2 connected between transistors Q22, Q23 and internal node N21.
Voltage switch circuit 315 has a P type MOS transistor Q24 having its gate connected to a node N22 and provided to connect power supply line 342 and internal node N21, and a P type MOS transistor Q25 and a N type MOS transistor Q26 connected in series between internal node N21 and ground line 344. The gates of transistors Q25 and Q26 are connected to the output node of inverter IV11.
According to such a construction, when the output of inverter IV11 is at the "H" level corresponding to an inactive state of boost control signal BST, voltage generation switch circuit 315 outputs power supply voltage Vcc to internal node N21. When the output of inverter IV11 is at the "L" level corresponding to an activate state of boost control signal BST, however, transistor Q24 turns off, internal node N21 and power supply line 342 are thus disconnected, and the output voltage of boost capacitance switch circuit 314 is transmitted to output transistor 330.
In boost capacitance switch circuit 314, when boost control signal BST is inactive, and the output of inverter IV11 is at the "H" level, the output of inverter IV12 attains the "L" level and transistor Q23 turns on, and therefore boost capacitor Cb1 is charged by a voltage difference between power supply voltage Vcc and the "L" level voltage output from inverter IV12. Further, boost capacitor Cb2 is charged by a voltage difference between power supply voltage Vcc and ground voltage Vss.
When the output of inverter IV11 changes to the "L" level in response to activation of boost control signal BST, charge stored in both boost capacitors Cb1, Cb2 or only charge stored in boost capacitor Cb1 is discharged to internal node N21 according to the voltage level of Vcc level signal LVL. Thus, the voltage level of internal node N21 has a value of the "H" level voltage output from inverter IV12 plus the boosted amount corresponding to the charge stored in one or more boost capacitors.
Vcc level signal LVL is set at the "L" level when power supply voltage Vcc is at most a prescribed level and at the "H" level when power supply voltage Vcc is higher than the prescribed level. When the output of inverter IV11 is at the "L" level according to activation of boost control signal BST, and signal LVL is at the "L" level, the voltage level of node N23 is at the power supply voltage Vcc level since transistors Q21 and Q22 turn on. That is, a value of power supply voltage Vcc plus the boosted voltage (.DELTA.Vb1+.DELTA.Vb2) by boost capacitors Cb1, Cb2 is output to internal node N21.
When signal LVL is at the "H" level, transistor Q22 turns off Thus, the voltage of node N23 is ground voltage Vss, and charge stored in boost capacitor Cb2 is not used to boost internal node N21.
According to such a construction, the capacitance of a boost capacitor can be switched equivalently at the power supply voltage Vcc level.
Voltage generation circuit 300 also includes gate boost circuit 320. When a boosted voltage is applied to the source of output transistor 330 by boost circuit 310 according to boost control signal BST, gate boost circuit 320 boosts the gate voltage of output transistor 330 to transmit the boosted voltage to voltage supply node 340.
According to the configuration of voltage generation circuit 300 described with reference to FIG. 8, the problem of excessive boosting of a word line voltage can be solved, even when a power supply voltage is high, by switching, according to the level of power supply voltage Vcc, the boosted amount of boosted voltage Vbst from power supply voltage Vcc when boost control signal BST is activated.
In the configuration of voltage generation circuit 300, however, the level of power supply voltage Vcc has always to be detected by a Vcc level detection circuit. Thus, current is consumed by the Vcc level detection circuit even during a standby period when a boosting operation is not required. Therefore, a standby current increases which in turn increases power consumption by the entire memory device.